(1) Field of the Invention
This invention relates to a circuit for generating scanning pulses, and more particularly to a circuit for generating scanning pulses which is constructed of a semiconductor integrated circuit. Further, this invention pertains to a pulse generator which generates pulses for selectively scanning sequentially and digitally a large number of photoelectric conversion elements disposed in an optical reader, a photosensor array of a facsimile, a solid-state imager, etc., especially to such scanning pulse generator which is constructed of an integrated circuit composed of MIS (Metal-Insulator-Semiconductor) insulated gate field-effect transistors etc.
(2) Description of the Prior Art
Heretofore, as a circuit for generating scanning pulses, there has been extensively utilized a shift register type scanning circuit wherein in order to sequentially scan a large number of photoelectric conversion elements in a linear or array arrangement, input pulses are delayed a fixed time and then delivered in succession by the use of two or more phases of clock pulses as illustrated in FIG. 1A. This figure is a circuit diagram of the first three stages of the shift register type scanning circuit employing MIS insulated gate field-effect transistors (hereinbelow, abbreviated to "MISTs").
Blocks G.sub.1 and G.sub.2 are generators for clock pulses .phi..sub.1 and .phi..sub.2 respectively, and a block G.sub.3 is a generator for input pulses V.sub.IN. V.sub.D indicates a D.C. power supply for drive, and V.sub.S indicates a reference voltage terminal which usually applies the earth voltage. Transistors Q.sub.1 and Q.sub.2 are load MISTs of the saturation mode which are formed by connecting the gates and drains thereof. Transistors Q.sub.3 and Q.sub.4 are driver MISTs. A circuit in which the source of the MIST Q.sub.1 and the drain of the MIST Q.sub.3, or the source of the MIST Q.sub.2 and the drain of the MIST Q.sub.4 are combined in series operates as an inverter. Transistors Q.sub.5 and Q.sub.6 are transfer MISTs.
Although the following description will be made by taking N-channel MISTs as an example and employing the positive logic (in which a positive high voltage is expressed by "1" and the earth voltage by "0"), quite the same applies to P-channel MISTs by inverting the signs of voltages. The input pulse V.sub.IN which is applied to the first stage inverter by the input pulse generator G.sub.3 is delayed a fixed time decided by the clock pulses .phi..sub.1 and .phi..sub.2, every passage through each stage by the transfer MISTs which are alternately turned "on" and "off" by the clock pulses .phi..sub.1 and .phi..sub.2. The delayed pulses appear at output terminals V.sub.01, V.sub.02 and V.sub.03 of the respective stages as illustrated in a timing diagram of FIG. 1B.
The shift register type scanning circuit utilizing the MISTs is suited to a semiconductor integrated circuit in such a point that all the circuit elements can be fabricated of the MISTs and that the fabricating process is comparatively simple. The density of integration and the available percentage are also enhanced easily. Since the operating margin is high and the deviations of the characteristics of the respective stages are small, the foregoing scanning circuit is very excellent as a scanning circuit which requires many stages of outputs.
The scanning circuit above described, however, has the following disadvantages:
1 Current flows through one of two stages of inverters at all times, so that the power dissipation is high.
2 Notwithstanding that the drivability of a load is determined by the MIST Q.sub.2 (or Q.sub.1), the channel width of the driver transistor MIST Q.sub.4 (or Q.sub.3) (accordingly, the size of the transistor) must be made large, so that a large area is occupied. More specifically, the output offset voltage becomes: ##EQU1## where V.sub.D : supply voltage,
g.sub.m (Q.sub.2): conductance of MIST Q.sub.2, PA1 g.sub.m (Q.sub.4): conductance of MIST Q.sub.4, PA1 L.sub.2 : channel width of MIST Q.sub.2, PA1 L.sub.4 : channel width of MIST Q.sub.4.
In order to make the offset small, the channel width L.sub.4 of the MIST Q.sub.4 must be made great, so that the area of the MIST Q.sub.4 increases.
3 The output signal voltage swing is small as compared with the supply voltage. The "0" level of the output does not become the ground potential (it becomes approximately V.sub.D .multidot.g.sub.m (Q.sub.2)/g.sub.m (Q.sub.4)), and the "1" level of the output does not become the potential of the power supply, either.
4 The deviation of the threshold voltage of the MIST Q.sub.4 has great influence.
Besides the scanning circuit shown in FIG. 1A, a shift register constructed of complementary MISTs (CMOS) has been devised. According to the CMOS circuit, the operating speed is high and the power dissipation is low, and the number of constituent elements per stage decreases. However, N-channel MISTs and P-channel MISTs must be integrated, and the manufacturing process becomes complicated. It is therefore desirable to construct the scanning circuit by the use of MISTs of either channel.
As still another type of scanning circuit, there has been known one which exploits the bootstrap effect of MISTs. FIG. 2A shows the scanning circuit exploiting the bootstrap effect as proposed by N. Koike being the inventor of this invention (refer to U.S. Ser. No. 764,841 filed Feb. 2, 1978 and German laid-open Pat. No. 2705429).
In FIG. 2A, Q.sub.10 indicates a MIST which serves to transfer an input pulse (level "1" or "0") supplied from an input pulse generator G.sub.3, under the control of a clock pulse; Q.sub.11 a charging MIST which is connected on the output side of the transfer MIST Q.sub.10 and which serves to deliver a scanning output pulse to an output side terminal V.sub.01 under the control of another clock pulse; and Q.sub.7 a discharging MIST which is connected between the output side of the charging MIST Q.sub.11 and an earth line and which serves to discharge charges stored in an output terminal circuit.
On the other hand, a driving MIST Q.sub.8 and a load MIST Q.sub.9 are connected in cascade between a power supply line V.sub.D and the earth line, and the gate of the discharging MIST Q.sub.7 is connected to the node N.sub.1 between both the MISTs Q.sub.8 and Q.sub.9. The node N.sub.2 between the transfer MIST Q.sub.10 and the charging MIST Q.sub.11 is connected to the gate of the driving MIST Q.sub.8. C.sub.B indicates a bootstrap capacitance which is connected between the source and gate of the charging MIST Q.sub.11.
FIG. 2B shows a timing chart of the clock pulses .phi..sub.1 and .phi..sub.2, the input pulse V.sub.IN and pulses at the node N.sub.2, the output terminal V.sub.01 and the node N.sub.1.
The scanning circuit of FIG. 2A is such that a unit circuit is made up of the five MISTs Q.sub.7, Q.sub.8, Q.sub.9, Q.sub.10 and Q.sub.11 and that the basic circuits are connected into many stages. FIG. 2C shows a timing chart of the clock pulse .phi..sub.1 and .phi..sub.2, the input pulse V.sub.IN and output pulses V.sub.01, V.sub.02 and V.sub.03.
This scanning circuit exploiting the bootstrap effect of MISTs has the advantage that a continuous current to hold the state of an inverter being otherwise existent can be removed, so the power dissipation is reduced. However, it has the disadvantage that noise in the bandwidth are prone to occur on account of the difference of the waveforms of the clock pulses .phi..sub.1 and .phi..sub.2 (attributed to the difference of pulse shaping units). The scanning circuit of FIG. 2A requires the five MISTs and one bootstrap capacitance of sufficiently large capacity as the fundamental constituent elements per stage and has not its construction simplified very much, so that a difficulty remains in point of the density of integration yet.
As the scanning circuit exploiting the bootstrap effect, there has also been one which is disclosed in U.S. Pat. No. 3,829,711. It also requires five MISTs as constituent elements per stage, which forms a difficulty in point of the density of integration.